Serial transmissions in which a clock signal is not transmitted are typically employed for data transmissions via high-speed interfaces, where the use of a synchronized source clock signal becomes unreliable and cost-intensive because an uncontrolled shift takes place between the data signals and between the data and clock signals. With interfaces of this kind, the clock signal is removed and each transmission channel is considered to be an independent data stream which requires an independent clock signal recovery at the receiver end.
A diagram of a serial transmission link of this kind is shown in FIG. 9. At the transmission end of such a transmission link, use is made of a multiplexer 43 to multiplex a synchronized data signal n to give a required transmission clock rate by means of a reference clock signal o of relatively low frequency, and to transmit the data signal n over the interface, i.e., transmission channel, 44. At the receiver end, the received signal is sampled by means of a sampling device 45 to allow a data signal p to be obtained. A clock signal q is also recovered. In a demultiplexing means 46, the sampled data signal p is demultiplexed with the help of the clock signal q in order to again obtain a synchronized data signal r having a lower clock rate and a clock signal s of correspondingly reduced frequency.
The process performed at the receiver end is also referred to as clock and data recovery (CDR). In the case of such transmissions it is desirable for the transmission link, and hence the components used for it, to operate over a wide frequency range and to exhibit low phase noise.
The bandwidth for clock signal recovery must be such that a drift or change in the phase of the received signal can be followed and the inherent noise must be so low that the sampling error remains low even when there is high jitter.
Conventional solutions for high-speed transceivers use two independent voltage-controlled oscillators (VCOs) for the transmission and reception sections to generate a transmission clock signal and a reception clock signal.
A typical layout for generating a transmission clock signal is shown in FIG. 10. In it, a reference signal a, which may for example be generated by a quartz oscillator, and a feedback signal b are fed to a phase detector or phase-frequency detector 1. From these, the phase-frequency detector 1 generates a phase-difference signal, which is filtered by a loop filter 2, thus producing a control signal for controlling a voltage-controlled oscillator 3. As a function of the control signal fed to it, the voltage-controlled oscillator 3 emits a transmission clock signal c which, via a frequency divider 5, is fed back again to the phase-frequency detector 1 as a feedback signal b. A phase locked loop of this kind generates a transmission clock signal c of a frequency which is higher by a given factor than the frequency of the reference signal a, with the given factor corresponding to the dividing factor of the frequency divider 5.
A typical layout for recovering a clock signal in a receiving device is shown diagrammatically in FIG. 11. A phase detector 47 compares the phase of an incoming data signal t with that of a feedback signal u and once again transmits a phase-difference signal to a loop filter 48, which generates a control signal for a voltage-controlled oscillator 49. The latter's output signal u is then used for sampling and demultiplexing the data and as a feedback signal for the phase locked loop. A transceiver contains both the arrangement shown in FIG. 10 and the one shown in FIG. 11.
If, as is generally the case, the transmission clock signal c and the reception clock signal u are not synchronized, this may lead to an interaction between the voltage-controlled oscillators 3, 49 and thus, possibly, to a beat and to increased noise in the voltage-controlled oscillator 3 of the transmission section. Also, at high clock rates, the implementation of clock signal recovery shown in FIG. 11 leads to difficulties in suppressing noise, to a relatively high current consumption and to the component tolerances having to meet severe demands.